EVAL-AD1852EB【PDF 5/14 页】24-Bit Stereo DAC Evaluation Board

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录362799

1页 2页 3页 4页 [5页]6页 7页 8页 9页

REV. 0

EVAL-AD1852EB

–5–

APPENDIX A

MODULE

IF_Logic

TITLE

‘AD1852 EVB Logic’

//===================================================================================

// FILE:

// REVISION DATE:

// REVISION BY:

// REVISION:

// PREVIOUS FILE: 1852r9.abl, AD1852v8.abl

// PREVIOUS DATE: 10-01-99

// PREVIOUS REVISION: 2.0

// ORIGINAL AUTHOR:

// BOARD REV.:

// DESCRIPTION:

// This chip selects between the External Data Interface header (J2) and the

// onboard CS8414 DIR (U2) for the AD1852 DAC input signals, depending upon

// the SPDIF/EXT switch position (S3). When the DIR is the selected signal

// source the digital audio signals, SDATA, BCLK and LRCLK also appear at the

// external Data Interface header (J2) as outputs.

// It also decodes the Interface Mode Switch(S5) and sets the interface mode

// pins for both the CS8414 DIR and the AD1852 DAC and corrects the CS8414

// output signals for LJ, RJ, and DSP modes, to match the signal requirements

// for the AD1852.

// It also decodes signals from LabView SPI port control software so that it

// can correctly set the interface mode pins for the CS8414 and correctly

// format the CS8414 output signal for LJ, RJ, and DSP modes. (This

// functionality is required when the SPI port is used to set the data format

// used by the DAC instead of setting it directly via the IDPM pins with the

// Interface Mode Switch, S5.)

// It also decodes the Deemphasis control signal from the CS8414 (U2) and

// DEEMPH switch(S4), enables and buffers the output master clock and the

// VERF signal from the CS8414.

// Finally, the CPLD buffers and drives the status LEDs.

//=============================================================================

LIBRARY ‘MACH’;

MACH_SLEW(FAST,2,MCLK:MCLKO);

1852ext.abl

11-01-99 (comment revisions on 2-9-00)

Brian Wachob

3.0 (plus comments)

Larry Hurst

This code is written for the “AD185_ REV 1” eval. boards

(with, of course, an AD1852 DAC installed on the eval. board)

DECLARATIONS

// IF_Logic DEVICE ‘M4-64/32-15VC’;

“INPUTS ———————————————————————————————————

// TDI, TCK, TMS pin 4, 7, 26; //JTAG I/P’s

SLCT_C, SLCT_B, SLCT_A pin 15, 19, 14; //Interface Mode Select

ISDATA, IMCLK, ILRCLK, IBCLK pin 1, 5, 9, 10; //DIR I/P’s

VERF, NPREEMPH, NDEEMPH pin 44, 8, 13; //DAC Control

SPDIF_EXT pin 12; //DAC Signal Source Select

ZR, ZL pin 24, 34; //DAC ZERO Signals

EMCLK pin 27; //External MCLK Input

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式